In manufacturing a semiconductor device, a semiconductor wafer is repeatedly subjected to a film forming process and a pattern etching process, in general. Design rules are becoming stricter every year in accordance with a recent increase in density and integration of semiconductor devices. For example, a very thin oxide film such as an insulator film of a capacitor structure is required to be much thinner, and have a higher insulation performance as well.
Although silicon oxide film and a silicon nitride film may be used as such insulation film, the recent trend is to use a metal oxide film having a higher insulation performance, such as tantalum oxide film (Ta2O5). The metal oxide film has a reliable insulation performance even if the film thickness is small.
When forming a tantalum oxide film, pentaethoxytantalum (Ta(OC2H5)5) (hereinafter referred to as “PET”), which is a metal alkoxide of tantalum, is used as a material for forming the film. PET is bubbled with helium gas or the like to be supplied into a process chamber of a vacuum atmosphere. Then, a tantalum oxide film is formed, by a CVD (Chemical Vapor Deposition), on a semiconductor wafer maintained at a relatively low process temperature, such as about 410° C., in the processing chamber.
FIG. 6 shows a capacitor structure of an MIM (Metal-Insulator-Metal) structure employing a tantalum oxide film. The capacitor structure is composed of films formed on a semiconductor wafer 2 of silicon substrate, which includes lower electrode film 4, an upper electrode film 8, both of which are made of metal such as Ru (ruthenium) or metal compound such as TiN (titanium nitride), and a high dielectric film 6 made of a high dielectric substance such as Ta2O5 (tantalum oxide) interposed between the lower and upper electrode films 4 and 8.
A film thickness of the high dielectric film 6 is about 8 to 12 nm when the film is used for a front end of an integrated circuit, and about 20 to 60 nm when used for a back end. The term “front end” refers to lower to middle layers of a multilayered integrated circuit, and the term “back end” refers to middle to upper layers of the same.
Recently, the use of the above MIM structure for a capacitor structure of the back end has been considered. However, in the aforementioned conventional MIM structure, although leakage current is sufficiently low if low operation voltage such as about ±1V is applied thereto, leakage current is considerably high if high operation voltage such as about ±5V is applied thereto.
In addition, a slight change in a capacity of the capacitor structure accompanied with a change of an applied voltage is inherently inevitable, but with aforesaid conventional MIM structure, change in the capacity of the capacitor structure accompanied with change in applied voltage is considerably large.